Jack received his master’s degree from National Chiao Tung University and started his first job at Nanya Technology 8-inch fab as Diffusion Engineer. He was a pioneer to join the setup of first 12-inch fab of Inotera as well as participating the two more fabs (F11A/B/C) expansion. Afterwards, he transferred to Micron in 2016. In Inotera and current company, Jack served in various areas in Equipment/Process (DF/Wet/PH), Quality, Technology Transfer, Max out/Cost down sponsor and in charge Program Office (SPMO) and PEE.
He experienced various positions as section manager, department manager, director, and senior director. Jack had taken care of HVM operation as Senior Director for two and half years. With more than 20 years of experience in semiconductor industry, Jack now oversees Quality and Yield enhancement as Senior Director. He is acclaimed for his sense of urgency, willingness to change, and proactiveness. In his free time, he enjoys gardening, swimming, movies, and table tennis.
WORK EXPERIENCE AND AWARDS
Micron Technology, Taiwan
Senior Director of Quality and Yield Enhancement (2022 - present)
HVM Senior Director (2019 - 2022)
PEE Division Director (2018 - 2019)
SPMO Division Director (2017 - 2018)
Process QE Senior Manager (2010 - 2017)
Diffusion/Wet/PH Process Senior Manager (2003 - 2010)
EDUCATIONAL BACKGROUND
Master in Mechanical Engineering, National Chiao Tung University, Taiwan
INSTRUCTION LANGUAGES
Mandarin
English
Job Positions
Product QE Intern (Taichung)
2 Vacancies
Co-Supervisor Information
Jason KUO
郭進森
Institution
Micron Technology
Division/Department
Micron Product QE & YE Department
Job Title
Director of OMT YE/PRODUCT QE/TCP
Brief Introduction of the Department
【Micron Product QE & YE Division】
Product QE Division contains Product Quality Assurance departments (PQA) & Taiwan Central probe (TCP) departments. The major responsibility of PQA is to ensure our product quality meeting customers specifications and quality requirements. This team also in charge of New Product Introduction (NPI), Product grade, Backend yield and quality/reliability improvement from pilot to HVM phase. In addition, MRB (Material review board)/RMA (Return Material Authorization) management with comprehensive data analysis and risk assessment to guard band micron product quality in order to meet customers requirement. TCP takes responses for wafer probing stability control, tool maintenance/recipe optimization to sustain tools stay at high utilization. This mission of TCP team to achieve wafer output meeting demand requirement by production dispatch optimization and capacity assessment.
YE Division contains Yield Enhancement and Failure Analysis departments that response for probe yield improvement and detect FAB process issue shortly by data analysis/mining to minimize impact. This teams also need to confirm failure mode with electrical characteristics and to find the root cause with physical failure analysis.
Department Staff Number
- More than 10 people
Internship Job Description
PQA:
- PTS(Probe To Ship) component level yield enhancement and detractors debug/improvement
- Product Grade improvement with repair density and disposition rule optimization
- NPI product qualification
- Product quality ARH/ABI/ABL and module HMB1/QMON dpm improvement
- In charge of RMA response and ensure manufacturing improvement/prevention
- Product WLR reliability monitoring and program development
TCP:
- Probe tool maintenance and sustain at high utilization
- Probe Contact mechanism and failure analysis Improvement
- Perform wafer output to meet demand
- Familiar production line flow and capacity calculation
- Optimize production line operation into smart factory
- Build up automation process and optimize decision making
- Crunch and dipso rule setup
YE:
- Data analysis of failure by explaining details of parametric, functional, margin bins and using ESDA information for yield improvement
- Using electrical localization tool (EMMI/OBIRCH/EOP/EOFM) and imaging/elements/Film quality analysis tools (SEM, FIB, TEM, EDX, SIMS) to identify the cause of failure and report the results to the engineer.
- Test program optimize and device characteristics understanding to support fab provide high quality DRAM meet customer request
- Summarize full yield pareto with improvement actions and implementation schedule
- Communicate with FAB engineers to understand expected failures and review analytical data.
Preferred Intern Education Level
- undergraduate students (third year and above) - Master students - Ph.D. students
Preferred Intern Skill Sets or Qualities
- Good understanding of basic semiconductor FAB process.
- Willingness to enhance basic knowledge of devices, processes and analytical equipment.
- Willingness to learn and take challenges.
- Ability to understand layout and structure.
- Ability to follow equipment operating procedures and rules.
- Ability to prioritize and work independently.
- Ability to analyze problems and provide resolution.
- Experience with SEM and TEM or FIB platforms a plus.
- Electrical device characteristics and comment on fail mode.
- Strong communication skills (written, verbal and presentation).
- Positive thinking.